1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which allows for testing all redundancy cells.
2. Description of the Related Art
A semiconductor memory device includes regular cells and corresponding redundancy cells. The redundancy cells are adapted to be substituted for defective regular cells and thus increase the yield in fabricating memory devices.
As the process of fabricating semiconductor memory devices becomes more complicated, cell defect rate increases. Accordingly, the probability of redundancy cells being substituted for the defective regular cells increases. Thus, it is increasingly important to check all redundancy cells for defects.
To guarantee the quality of redundancy cells, the redundancy cells are tested at the same level as regular cells. In particular, for post-package repair methods, the redundancy cells are substituted for the regular cells even after a wafer is packaged, as well as after the wafer is tested. Thus, it is necessary to test all redundancy cells even after packaging completion in order to check the quality of the device.
However, conventional semiconductor memory devices only allow for testing fuse-programmed redundancy cells by a fuse programming circuit, not non-fuse-programmed redundancy cells. Consequently, it is impossible to test all the redundancy cells of conventional semiconductor memory devices. FIG. 1 illustrates the configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a memory cell array 11, a redundancy memory cell array 12, a pre row decoder 13, a row decoder 14, a pre column decoder 15, a column decoder 16, a row fuse controller 17, and a redundancy row decoder 18.
The memory cell array 11 includes a plurality of regular cells. Data is written/read to/from regular cells selected by word line enable signals from the row decoder 14 and column selection signals from the column decoder 16.
The redundancy memory cell array 12 includes a plurality of redundancy cells corresponding respectively to the plurality of regular cells in the memory cell array 11. Data is written/read to/from redundancy cells selected by word line enable signals from the redundancy row decoder 18 and column selection signals from the column decoder 16.
The pre row decoder 13 pre-decodes a plurality of row address signals RAab to generate a plurality of pre-decoded row address signals PRAcd. The row decoder 14 is enabled when it does not receive a row repair signal repair_R, and decodes the plurality of pre-decoded row address signals PRAcd to generate the word line enable signals for selecting regular cells included in the memory cell array 11.
The pre column decoder 15 pre-decodes a plurality of column address signals CAgh to generate a plurality of pre-decoded column address signals PCAij. The column decoder 16 decodes the plurality of pre-decoded column address signals PCAij to generate column selection signals for selecting the regular cells or the redundancy cells.
The row fuse controller 17 programs a plurality of fuses according to row addresses of defective regular cells (hereinafter, referred to as “defective cells”), which are identified in wafer testing and post-packaging testing. When addresses indicated by the input pre-decoded row address signals PRAcd match programmed row addresses, the row fuse controller 17 generates a row repair signal repair_R for enabling repair operation and row fuse signals RFef for selecting redundancy cells to be substituted for defective cells.
In this case, a plurality of fuses in the row fuse controller 17 may be implemented by laser beam-cut laser fuses or electrically cut electric fuses. Each of the plurality of fuses is selectively cut to be programmed.
The redundancy row decoder 18 is enabled when receiving the row repair signal repair_R and decodes a plurality of row fuse signals RFef to generate word line enable signals for selecting redundancy cells in the row redundancy memory cell array 12.
Hereinafter, operation of the semiconductor memory device will be described with reference to FIG. 1.
It is assumed that row addresses of defective cells are programmed in the row fuse controller 17 and row addresses RAab for selecting programmed row addresses are input from the exterior.
When receiving the plurality of row addresses RAab, the pre row decoder 13 generates a plurality of decoded row addresses DRAcd. When receiving the decoded row addresses PRAcd for selecting the programmed row address, the row fuse controller 17 generates a row repair signal repair_R for enabling repair operation and row fuse signals RFef for selecting redundancy cells to be substituted for defective cells.
The row decoder 14 is disabled in response to the row repair signal repair_R, and the redundancy row decoder 18 generates word line select signals for selecting redundancy cells to be substituted for defective cells in response to the row repair signal repair_R and the row fuse signals RFef.
Accordingly, the redundancy memory cell array 12 selects the redundancy cell in response to the word line select signals from the row decoder 14 and the column selection signal from the column decoder 16.
In order to test the selected redundancy cell in the semiconductor memory device, electric stress is applied to the selected redundancy cell or an active operation (e.g., read or write operation) is performed through the selected redundancy cell.
As such, since the conventional semiconductor memory device has no means for selecting a redundancy cell to be tested, only redundancy cells selectable through fuse programming are selected and tested.
In this manner, it is only possible to check whether any fuse-programmed redundancy cells are defective, but not non-fuse-programmed redundancy cells.
Consequently, in the conventional semiconductor memory device, a defective redundancy cell may be substituted for another defective cell, which significantly degrades reliability of the repair operation.